This invention relates to a bus controller for a computer system such as a multi-processor system, for example, in which first and second processing sets (each of which may comprise one or more processors) communicate with an I/O device bus via a bridge.
The application finds particular but not exclusive application to fault tolerant computer systems where two or more processor sets need to communicate in lockstep with an I/O device bus via a bridge.
In such a fault tolerant computer system, an aim is not only to be able to identify faults, but also to provide a structure which is able to provide a high degree of system availability and system resilience to internal or external disturbances. In order to provide high levels of system resilience to internal disturbances, such as a processor failure or a bridge failure for example, it would be desirable for such systems automatically to control access to and from a device that might appear to be causing problems.
Automatic access control provides significant technical challenges in that the system has not only to monitor the devices in question to detect errors, but also has to provide an environment where the system as a whole can continue to operate despite a failure of one or more of the system components. In addition, the controller must also deal with any outstanding requests issued by components of the computer system and this is typically problematic as bus protocols, such as PCI for example, typically don't support error termination at all stages of operation.
Accordingly, an aim of the present invention is to address these technical problems.